1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having memory cells, and more particularly to a technology for performing write operations at high speed.
2. Description of the Related Art
FIG. 1 shows the configuration of the main parts in a semiconductor integrated circuit of this type. In the drawings, those signal lines shown by thick lines are composed of a plurality of lines each. Some of the blocks connected with the thick lines are composed of a plurality of circuits.
The semiconductor integrated circuit comprises an input/output control unit 1, a core control unit 2, and a memory core 3.
The input/output control unit 1 comprises a clock buffer 4, a command buffer 5, a row address buffer 6, a column address buffer 7, an input/output buffer 8, and a command decoder 9.
The clock buffer 4 receives a clock signal CLK, and outputs an internal clock signal ICLK. The command buffer 5 accepts a command signal CMD in synchronization with the internal clock signal ICLK, and outputs the accepted signal as an internal command signal ICMD.
The row address buffer 6 accepts a row address signal RAD in synchronization with the internal clock signal ICLK, and outputs the accepted signal as an internal row address signal IRAD. The column address buffer 7 accepts a column address signal CAD in synchronization with the internal clock signal ICLK, and outputs the accepted signal as an internal column address signal ICAD.
The input/output buffer 8, in a write operation, accepts a data signal DQ in synchronization with the internal clock signal ICLK, and outputs the same in the form of an internal data signal IDQ. In a read operation, the input/output buffer 8 accepts an internal data signal IDQ in synchronization with the internal clock signal ICLK, and outputs the accepted signal as a data signal DQ.
The command decoder 9 receives the internal clock signal ICLK and the internal command signal ICMD, decodes the command, and generates control signals RDZ, WRZ, and the like for controlling the main circuits of the semiconductor integrated circuit. Here, the control signal RDZ is generated when a command signal CMD corresponding to a read operation is supplied. The control signal WRZ is generated when a command signal CMD corresponding to a write operation is supplied.
The core control unit 2 comprises an RAS generator 10, a precharge generator 11, a control circuit 12, a predecoder 13, a block decoder 14, a CAS generator 15, a control circuit 16, a predecoder 17, a word decoder 18, a BRSZ generator 19, a sense amplifier generator 20, a column decoder 21, a read control circuit 22, a write control circuit 23, a read buffer 24, and a write buffer 25. Of the circuits mentioned above, the RAS generator 10, control circuit 12, word decoder 18, BRSZ generator 19, sense amplifier generator 20, and column decoder 21 function as a timing control unit 26.
The RAS generator 10 receives the control signals RDZ and WRZ, and the precharging signal PREZ from the precharge generator 11, and outputs a row controlling signal RASZ. The precharge generator 11 receives the row controlling signal RASZ, and outputs the precharging signal PREZ after a predetermined time.
The control circuit 12 receives the row controlling signal RASZ, generates a plurality of control signals RCON, and outputs the respective control signals RCON to the word decoder 18, the BRSZ generator 19, and the sense amplifier generator 20.
The predecoder 13 receives the internal row address signal IRAD, and outputs a predecode signal RPDEC. The block decoder 14 receives part of the predecode signal RPDEC, generates a decode signal, and outputs this decode signal to the word decoder 18, the BRSZ generator 19, and the sense amplifier generator 20.
The CAS generator 15 receives the control signals RDZ and WRZ, and outputs a column controlling signal CASZ. The control circuit 16 receives the column controlling signal CASZ, generates a plurality of control signals CCON, and outputs the respective control signals CCON to the column decoder 21, the read control circuit 22, and the write control circuit 23.
The predecoder 17 receives the internal column address signal ICAD, and outputs a predecode signal CPDEC.
The read control circuit 22 receives the predecode signal CPDEC and the control signal CCON, and outputs a read data controlling signal RD. The write control circuit 23 receives the predecode signal CPDEC and the control signal CCON, and outputs a write data controlling signal WD.
The read buffer 24 receives the common date signals DBZ and DBX from the memory core 3 in synchronization with the read data controlling signal RD, and outputs the same in the form of the internal data signal IDQ. The write buffer 25 receives the internal data signal IDQ in synchronization with the write data controlling signal WD, and outputs the same to the memory core 3 in the form of the common data signals DBZ and DBX. Here, the common data signals DBZ and DBX are complementary signals.
The word decoder 18 receives a predetermined control signal RCON, the predecode signals RPDEC and CPDEC, and the decode signal from the block decoder 14, generates a word line signal WLZ, and outputs the generated signal to the memory core 3.
The BRSZ generator 19 receives a predetermined control signal RCON, the predecode signals RPDEC and CPDEC, and the decode signal from the block decoder 14, generates a bit line controlling signal BRSZ, and outputs the generated signal to the memory core 3.
The sense amplifier generator 20 receives a predetermined control signal RCON, the predecode signals RPDEC and CPDEC, and the decode signal from the block decoder 14, generates a sense amplifier activating signal LEZ, and outputs the generated signal to the memory core 3.
The column decoder 21 receives the control signal CCON and the predecode signal CPDEC, generates a column selecting signal CLZ, and outputs the generated signal to the memory core 3.
The memory core 3 comprises a plurality of memory cells MC which are connected to word lines WL and bit lines BL (/BL) arranged vertically and horizontally. This example uses a DRAM memory core 3.
FIG. 2 shows the main parts of the memory core 3.
The memory core 3 comprises column switches 3a and 3b consisting of an nMOS, a sense amplifier 27, an nMOS 3c for equalization, nMOSs 3d and 3e for precharge, and a memory cell MS, which are connected to complementary bit lines BL and /BL.
Either the sources or the drains of the column switches 3a and 3b are connected to the bit lines BL and /BL, respectively. The others are connected to the common data signals DBZ and DBX, respectively. The gates of the column switches 3a and 3b receive the column selecting signal CLZ.
The sense amplifier 27 comprises: a CMOS inverter consisting of a pMOS 27a and an nMOS 27b; a CMOS inverter consisting of a PMOS 27c and an nMOS 27d; and a pMOS 27e and nMOS 27f for supplying a driving voltage to the sources of the respective CMOS inverters. The inputs and outputs of the CMOS inverters are connected with each other, and the outputs are connected to the bit lines BL and /BL separately. The pMOS 27e has the drain connected to the sources of the pMOS 27a and pMOS 27c, and the source connected to a power supply line VDD. The gate of the PMOS 27e is supplied with the sense amplifier activating signal LEZ through an inverter 27g. The nMOS 27f has its drain connected to the nMOS 27b and nMOS 27d, and the source connected to a ground line VSS. The gate of the nMOS 27f is supplied with the sense amplifier activating signal LEZ.
The source and the drain of the nMOS 3c are connected to the bit lines BL and /BL, respectively. Either the sources or the drains of the nMOSs 3d and 3e are connected to the bit lines BL and /BL, respectively. The others are connected to a precharging line VPR. The gates of the nMOSs 3c, 3d, and 3e receive the bit line controlling signal BRSZ.
The memory cell MS consists of an nMOS 28a for data transmission and a capacitor 28b. The gate of the nMOS 28a receives the word line signal WLZ.
FIG. 3 shows the main parts of the timing control unit 26.
The timing control unit 26 receives the precharging signal PREZ and the control signals RDZ and WRZ, and generates the bit line controlling signal BRSZ, the word line signal WLZ, the sense amplifier activating signal LEZ, and the column selecting signal CLZ with predetermined timings.
The timing control unit 26 comprises a delay circuit 26a consisting of eight inverters connected in cascade, a delay circuit 26b consisting of 11 inverters connected in cascade, a two-input NAND gate 26c, an inverter 26d, a two-input NOR circuit 26e, a delay circuit 26f consisting of four inverters connected in cascade, a two-input OR circuit 26g, and a CLZ generating circuit 26h.
The CLZ generating circuit 26h consists of a two-input NAND gate, three inverters, and a two-input NOR gate connected in cascade. The CLZ generating circuit 26h generates a High pulse (the column selecting signal CLZ) in accordance with the delay time of its inverters a predetermined time after the rising edges of the received signals.
The delay circuit 26a receives the precharging signal PREZ, and outputs the signal delayed to the delay circuit 26b and the NOR circuit 26e.
The OR circuit 26g receives the control signals RDZ and WRZ, and outputs the received signals as an enable signal ENZ.
The NAND gate 26c receives the enable signal ENZ and the output of the delay circuit 26b, and outputs the bit line controlling signal BRSZ.
The NOR circuit 26e receives the output signal of the delay circuit 26a and, through the inverter 26d, the inverted signal of the enable signal ENZ, and outputs the word line signal WLZ.
The delay circuit 26f receives the word line signal WLZ, and outputs the sense amplifier activating signal LEZ.
The CLZ generating circuit 26h receives the enable signal ENZ and the sense amplifier activating signal LEZ, and outputs the column selecting signal CLZ.
FIG. 4 shows the timings of the main signals in a write operation.
Initially, the semiconductor integrated circuit accepts a write command (WCMD) and the data signal DQ, along with the row address signal RAD and column address signal CAD whose waveforms are not shown, in synchronization with the rise of the clock signal CLK. The command decoder 9 shown in FIG. 1 receives the write command, and outputs the control signal WRZ (FIG. 4(a)). The input/output buffer 8 outputs the accepted data signal DQ as the internal data signal IDQ (FIG. 4(b)).
The precharge generator 11 shown in FIG. 1 receives the row controlling signal RASZ output from the RAS generator 10, and turns the precharging signal PREZ to high level after a predetermined time (FIG. 4(c)).
The NAND gate 26c in the timing control unit 26 shown in FIG. 3 receives the high level of the control signal WRZ, and turns the bit line controlling signal BRSZ to low level (FIG. 4(d)).
Likewise, the NOR circuit 26e receives the high level of the control signal WRZ, and turns the word line signal WL to high level (FIG. 4(e)). Here, by a boosting circuit not shown, the word line signal WL is set to have a voltage higher than that of other high-level signals. Besides, the word lines WL in the memory core 3 shown in FIG. 1 have greater wiring lengths so that their wiring resistance and load capacitance are large. Therefore, the word line signal WLZ makes gentler shifts as compared to the other signals.
The memory cell MC shown in FIG. 2 receives the high level of the word line signal WLZ, and turns the nMOS 28a on. The data (storage charge) retained in the memory cell MC are shared in accordance with the capacitance ratio between this memory cell MC and the bit line BL (or /BL). Thus, the bit line BL (or /BL) varies in voltage (FIG. 4(f)).
Then, the delay circuit 26f shown in FIG. 3 receives the word line signal WLZ, and turns the sense amplifier activating signal LEZ to high level (FIG. 4(g)). The sense amplifier 27 shown in FIG. 2 is activated under the high level of the sense amplifier activating signal LEZ, so that the weak potential difference between the bit lines BL and /BL is amplified (FIG. 4(h)). That is, the data retained in the memory cell MC are amplified before execution of a write operation.
Then, the CLZ generating circuit 26h shown in FIG. 3 receives the high level of the sense amplifier activating signal LEZ, and sets the column selecting signal CLZ to high level for a predetermined period (FIG. 4(i)). The column switches 3a and 3b shown in FIG. 2 are turned on under the high level of the column selecting signal CLZ, so that the common data signals DBZ and DBX, or the write data, are transmitted to the bit lines BL and /BL, respectively (FIG. 4(j)). Here, when the data output from the memory cell MC and the common data signals DBZ and DBX are inverse in logic, a signal inverting operation is performed. Then, the common data signals DBZ and DBX or the write data are written to the memory cell MC.
Subsequently, the NOR circuit 26e shown in FIG. 3 receives the precharging signal PREZ transmitted through the delay circuit 26a, and turns the word line signal WLZ to low level (FIG. 4(k)). The low level of the word line signal WLZ turns off the nMOS 28a in the memory cell MC to finish writing data.
The delay circuit 26f receives the word line signal WLZ, and turns the sense amplifier activating signal LEZ to low level (FIG. 4(l)). The sense amplifier 27 shown in FIG. 2 is inactivated under the low level of the sense amplifier activating signal LEZ, whereby the amplifying operation to the common data signals DBZ and DBX transmitted to the bit lines BL and /BL is completed.
Then, the NAND gate 26c shown in FIG. 3 receives the inverted signal of the precharging signal PREZ transmitted through the delay circuits 26a and 26b, and turns the bit line controlling signal BRSZ to high level (FIG. 4 (m)). The nMOSs 3c, 3d, and 3e shown in FIG. 2 are turned on under the high level of the bit line controlling signal BRSZ. The bit lines BL and /BL are connected to the precharging line VPR, and equalized at the same time. Then, the bit lines BL and /BL are precharged to complete the write operation (FIG. 4(n)).
In the write operation of this example, the cycle time tRC, which is a period from the falling edge of the bit line controlling signal BRSZ to the precharge of the bit lines BL and /BL, is 40 ns.
FIG. 5 shows the timings of the main signals in a read operation.
Initially, the semiconductor integrated circuit accepts a read command (RCMD) along with the row address signal RAD and column address signal CAD whose waveforms are not shown, in synchronization with the rising edge of the clock signal CLK. The command decoder 9 shown in FIG. 1 receives the read command, and outputs the control signal RDZ (FIG. 5(a)).
The precharge generator 11 receives the row controlling signal RASZ output from the RAS generator 10, and turns the precharging signal PREZ to high level after a predetermined time (FIG. 5(b)).
The control signal RDZ is output at the same timing as that of the control signal WRZ in the write operation described above. Due to this, the circuits in the timing control unit 26 shown in FIG. 3 make the same operations as those in the write operation. Therefore, the bit line controlling signal BRSZ, the word line signal WLZ, the sense amplifier activating signal LEZ, and the column selecting signal CLZ show the same waveforms as those in the write operation (FIG. 4).
The memory cell MC shown in FIG. 2 receives the high level of the word line signal WLZ, and turns the nMOS 28a on. The data retained in the memory cell MC are output to the bit line BL (or /BL) as a weak signal (FIG. 5(c)).
The sense amplifier 27 is activated under the high level of the sense amplifier activating signal LEZ, thereby amplifying the level of the weak signal on the bit lines BL and /BL (FIG. 5(d)).
The column switches 3a and 3b are turned on under the high level of the column selecting signal CLZ, so that the signal on the bit lines BL and /BL is output as the common data signals DBZ and DBX.
The input/output buffer 8 shown in FIG. 1 outputs the common data signals DBZ and DBX (the internal data signal IDQ) output from the read buffer 24, to the chip exterior as the data signal DQ (FIG. 5(e)). Then, the read operation is completed.
In the read operation of this example, the cycle time tRC, or the period from the falling edge of the bit line controlling signal BRSZ to the precharge of the bit lines BL and /BL, is 40 ns. In fact, a read operation can be made faster than a write operation. The cycle time tRC for a read operation is, however, made identical to the cycle time tRC for a write operation with the ease of use for users considered.
By the way, a conventional semiconductor integrated circuit, in write operations, amplifies the data output from memory cells MC before supplying write data to bit lines BL and /BL. This requires the inverting operations to the data irrelevant to the write data in the write operations, causing a problem of extended write time.
In addition, the write cycle time and the read cycle time, being the operating specifications, are made identical with each other for the sake of higher usability. Therefore, when the write cycle time is extended in accordance with the possible write time, the read cycle time needs to be extended as well. That is, a longer write time requires increases in the cycle times including that of a read operation. This means needless circuit operations, thereby increasing the power consumption.
Japanese Patent Laid-Open Publication No. Hei 2-226581 discloses an example of inputting write data before the sense amplifier completes the amplifying operation (that is, in the amplifying operation). In this example, the write data are input after the sense amplifier operates to start amplifying the previous data in the memory cell. This entails the inverting operation to the previous data amplified. The operating timings of the internal circuits in the semiconductor integrated circuit vary with temperature and voltage. Therefore, in the cases where the write data are input in the amplifying operations of the sense amplifier, the write operations are not shortened enough and the power consumption is sufficiently reduced in the worst conditions.